Model and Design of Improved Current Mode Logic Gates: Differential and Single-Ended

CHAPTER 1 INTRODUCTION
1.1 Background1.2 Available Literature 1.2.1 Various CML topologies1.2.2 Modeling and Design Approaches1.2.3 System Application1.3 Organization of the Book
CHAPTER 2 CML GATES: BASIC CONCEPTS
2.1 Introduction2.2 Basic Concepts2.3 Differential CML Gates2.3.1 Operation of the differential CML inverter 2.3.2 Analysis of the differential CML inverter 2.3.2.1 Static model2.3.2.2 Delay model2.3.3 Design of the differential CML inverter2.3.4 Realization of the basic gates2.4 Single-ended CML Gates2.4.1 Operation of the PFSCL inverter 2.4.2 Analysis of the PFSCL inverter 2.4.2.1 Static model2.4.2.2 Delay model2.4.3 Design of the PFSCL inverter2.4.4 Realization of the basic gates2.5 Concluding Remarks
CHAPTER 3 DIFFERENTIAL CML GATES WITH MODIFIED PDN
3.1 Introduction3.2 Literature Survey3.3 New Appraoch3.4 Improved Combinational Gates with Modified PDN3.4.1 Operation of the improved XOR gate3.4.2 Analysis of the improved XOR gate3.4.2.1 Static model3.4.2.2 Delay model3.4.3 Design of the improved XOR gate3.4.4 Performance comparison3.4.4.1 High speed design3.4.4.2 Power efficient design3.4.4.3 Low power design3.5 Improved Sequential Gates with Modified PDN 3.5.1 Operation of the improved D latch3.5.2 Analysis of the improved D latch 3.5.2.1 Static model3.5.2.2 Delay model3.5.3 Design of the improved D latch3.5.4 Performance comparison3.5.4.1 High speed design3.5.4.2 Power efficient design3.5.4.3 Low power design3.6 Concluding Remarks
CHAPTER 4 CML GATES WITH MODIFIED CURRENT SOURCE
4.1 Introduction4.2 Survey of the Current Source Modifications4.3 Dynamic Current Source4.3.1 Existing NN-dynamic current source4.3.2 New NP-dynamic current source4.4 Improved Differential CML Gates with NP-dynamic current source4.4.1 Operation of the D-MCML-NP inverter4.4.2 Design of the D-MCML-NP inverter4.4.3 Power consumption analysis4.5 Improved PFSCL Gates with NN-dynamic current source 4.5.1 Operation of the D-PFSCL-NN inverter 4.5.2 Design of the D-PFSCL-NN inverter 4.5.3 Power consumption analysis4.6 Improved PFSCL Gates with NP- dynamic current source4.6.1 Operation of the D-PFSCL-NP inverter4.6.2 Design of the D-PFSCL-NP inverter4.6.3 Power consumption analysis4.7 Multi-stage Applications4.7.1 Existing self-timed buffer4.7.2 Improved self-timed buffer4.8 Performance Comparison4.8.1 Performance comparison of the differential D-CML gates4.8.2 Performance comparison of the D-PFSCL gates4.9 Concluding Remarks
CHAPTER 5 CML GATES WITH MODIFIED LOAD
5.1 Introduction5.2 Available Loads5.3 New load (NP-Load)5.3.1 Analysis of the NP-load5.3.2 Resistance of the NP-load5.4 Improved Differential CML Gates with Modified Load5.4.1 Operation of the MCML-CC inverter5.4.2 Analysis of the MCML-CC inverter5.4.2.1 Static model5.4.1.1 Delay model5.4.3 Design of the MCML-CC inverter5.4.4 Perf