Direct Transistor-Level Layout for Digital Blocks

Name: Direct Transistor-Level Layout for Digital Blocks
Brand: Springer-Verlag New York Inc.
SKU: 9781475779516
Price: 38234 HUF
Availability: InStock

Szerző: Prakash Gopalakrishnan, Rob A. Rutenbar

Nyelv:

Kötés: Puha kötésű

Kiadó: Springer-Verlag New York Inc.

Elérhetőség: Beszállítói készleten

Küldés 5-8 napon belül

38 234 Ft

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately,...

Információk a könyvről

Szerző

Prakash Gopalakrishnan, Rob A. Rutenbar

Nyelv

Angol

Kötés

Könyv - Puha kötésű

Kiadva

2013

oldal

125

EAN

9781475779516

ISBN

1475779518

Enbook ID

05185625

Kiadó

Springer-Verlag New York Inc.

Súly

225

Méretek

155 x 235 x 8

Teljes leírás

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library.§Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability.§The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.§Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.

Érdekelheti

Azok a vásárlók, akik ezt a könyvet megvásárolták, a következőket is megvásárolták

Leggyakrabban keresett

Categories

Authors

Publishers

Termékek

Termékek

Leggyakrabban keresett

Categories

Authors

Publishers

Termékek

Termékek

Direct Transistor-Level Layout for Digital Blocks

Információk a könyvről

Teljes leírás

Érdekelheti

Azok a vásárlók, akik ezt a könyvet megvásárolták, a következőket is megvásárolták