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Könyv Formal Equivalence Checking and Design Debugging Shi-Yu Huang

Formal Equivalence Checking and Design Debugging

Szerző: Shi-Yu Huang, Kwang-Ting (Tim) Cheng
Nyelv: Angol
Kötés: Puha kötésű
Kiadó: Springer-Verlag New York Inc.
Elérhetőség: Beszállítói készleten
Küldés 5-8 napon belül
69 221 Ft
Formal Equivalence Checking and Design Debugging covers two major topics in design verification: log...

Információk a könyvről

Szerző
Shi-Yu Huang, Kwang-Ting (Tim) Cheng
Nyelv
Angol
Kötés
Könyv - Puha kötésű
Kiadva
2012
oldal
229
EAN
9781461376064
ISBN
1461376068
Enbook ID
06796998
Kiadó
Springer-Verlag New York Inc.
Súly
391
Méretek
155 x 235 x 14

Teljes leírás

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. §The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. §From the Foreword: §`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley

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